PIC16F777-E/ML【PDF 60/231 页】IC PIC MCU FLASH 8KX14 44QFN

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Sheet目录3873

56页 57页 58页 59页 [60页]61页 62页 63页 64页

PIC18F2X1X/4X1X

DS39636D-page 158

2009 Microchip Technology Inc.

16.3.5

MASTER MODE

The master can initiate the data transfer at any time

because it controls the SCK. The master determines

when the slave (Processor 2, Figure 16-2) is to

broadcast data by the software protocol.

In Master mode, the data is transmitted/received as

soon as the SSPBUF register is written to. If the SPI

interface is only going to receive, the SDO output could

be disabled (programmed as an input). The SSPSR

SDI pin at the programmed clock rate. As each byte is

received, it will be loaded into the SSPBUF register as

if a normal received byte (interrupts and status bits

appropriately set). This could be useful in receiver

applications as a “Line Activity Monitor” mode.

The clock polarity is selected by appropriately

programming the CKP bit (SSPCON1<4>). This then,

would give waveforms for SPI communication as

shown in Figure 16-3, Figure 16-5 and Figure 16-6,

where the MSB is transmitted first. In Master mode, the

SPI clock rate (bit rate) is user programmable to be one

of the following:

FOSC/4 (or TCY)

FOSC/16 (or 4 TCY)

FOSC/64 (or 16 TCY)

Timer2 output/2

This allows a maximum data rate (at 40 MHz) of

10.00 Mbps.

Figure 16-3 shows the waveforms for Master mode.

When the CKE bit is set, the SDO data is valid before

there is a clock edge on SCK. The change of the input

sample is shown based on the state of the SMP bit. The

time when the SSPBUF is loaded with the received

data is shown.

FIGURE 16-3:

SPI MODE WAVEFORM (MASTER MODE)

SCK

(CKP = 0

SCK

(CKP = 1

SCK

(CKP = 0

SCK

(CKP = 1

4 Clock

Modes

Input

Sample

Input

Sample

SDI

bit 7

bit 0

SDO

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

bit 7

SDI

SSPIF

(SMP = 1)

(SMP = 0)

(SMP = 1)

CKE = 1)

CKE = 0)

CKE = 1)

CKE = 0)

(SMP = 0)

Write to

SSPBUF

SSPSR to

SSPBUF

SDO

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

(CKE = 0)

(CKE = 1)

Next Q4 Cycle

after Q2

↓

bit 0

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